{"id":1118,"date":"2023-03-29T14:04:05","date_gmt":"2023-03-29T12:04:05","guid":{"rendered":"http:\/\/www.univ-oeb.dz\/RELACS\/?page_id=1118"},"modified":"2023-06-17T15:28:16","modified_gmt":"2023-06-17T14:28:16","slug":"equipe-1","status":"publish","type":"page","link":"https:\/\/www.univ-oeb.dz\/RELACS\/equipe-1\/","title":{"rendered":"Team 1: RTESMPEFVS"},"content":{"rendered":"
R<\/span>eal T<\/span>ime E<\/span>mbedded S<\/span>ystems M<\/span>odeling, P<\/span>erformances E<\/span>stimation, F<\/span>ormal V<\/span>erification and S<\/span>ynthesis<\/strong><\/h5>\n
\n

The design of r<\/strong>eal-t<\/strong>ime e<\/strong>mbedded s<\/strong>ystems (RTES<\/strong>) is a current topic that requires collaboration between several fields such as computer science, electronics, physics, mechanics, and even biology. Therefore, it is a multidisciplinary field<\/strong>.<\/span><\/p>\n

RTES is characterized as a heterogeneous complex system in the sense that it encompasses both hardware and software. It may contain a digital and\/or analog component and is subject to hard or soft real-time constraints, as well as strict spatial and energy constraints.<\/span><\/p>\n

The usual approach for designing such systems is Co-design<\/strong>, in which both hardware and software teams work synergistically from the early stages of the lifecycle by establishing an abstract model. Through successive refinements<\/strong>, they proceed towards physical implementation, involving activities such as simulation, performance estimation, formal verification, and prototyping, which are typically carried out on reconfigurable FPGA architectures.<\/span><\/p>\n

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Objectives<\/strong><\/span><\/h5>\n

Our goal is to develop an environment for the design of real-time embedded systems. This environment integrates a collection of tools that collaborate to perform the following tasks:<\/span><\/p>\n

    \n
  • Modeling of structural, dynamic, and temporal aspects, with a focus on the MARTE UML<\/strong> profile.<\/span><\/li>\n
  • Design space exploration, performance estimation, and optimization.<\/span><\/li>\n
  • Simulation and formal verification, with a focus on the RT-Maude<\/strong> language.<\/span><\/li>\n
  • Prototyping, targeting reconfigurable FPGA architectures and synthesis.<\/span><\/li>\n<\/ul>\n
    \n

    Scientific\u00a0<\/strong>F<\/strong>oundations\u00a0<\/strong><\/p>\n

    In the context of RTES engineering, research revolves around several complementary and current themes:<\/span><\/p>\n

      \n
    • Modeling of real-time embedded systems, with a focus on the MARTE\u00a0UML<\/span><\/strong>\u00a0profile.<\/span><\/span><\/li>\n
    • Performance estimation and optimization.<\/span><\/li>\n
    • Simulation, with a focus on SystemC<\/strong>.<\/span><\/li>\n
    • Formal verification, with a focus on RT-Maude<\/strong>.<\/span><\/li>\n
    • Prototyping on FPGA<\/strong>s.<\/span><\/li>\n
    • Synthesis, with a focus on VHDL<\/strong> for the hardware part and C<\/strong> for the software part.<\/span><\/li>\n<\/ul>\n
      \n
      Projects:<\/strong><\/span><\/h5>\n
      \n
      Publications:<\/strong><\/span><\/h5>\n
      \n
      Members:<\/strong><\/span><\/h5>\n","protected":false},"excerpt":{"rendered":"

      Real Time Embedded Systems Modeling, Performances Estimation, Formal Verification and…<\/p>\n","protected":false},"author":1,"featured_media":1259,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"_links":{"self":[{"href":"https:\/\/www.univ-oeb.dz\/RELACS\/wp-json\/wp\/v2\/pages\/1118"}],"collection":[{"href":"https:\/\/www.univ-oeb.dz\/RELACS\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/www.univ-oeb.dz\/RELACS\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/www.univ-oeb.dz\/RELACS\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/www.univ-oeb.dz\/RELACS\/wp-json\/wp\/v2\/comments?post=1118"}],"version-history":[{"count":5,"href":"https:\/\/www.univ-oeb.dz\/RELACS\/wp-json\/wp\/v2\/pages\/1118\/revisions"}],"predecessor-version":[{"id":1282,"href":"https:\/\/www.univ-oeb.dz\/RELACS\/wp-json\/wp\/v2\/pages\/1118\/revisions\/1282"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/www.univ-oeb.dz\/RELACS\/wp-json\/wp\/v2\/media\/1259"}],"wp:attachment":[{"href":"https:\/\/www.univ-oeb.dz\/RELACS\/wp-json\/wp\/v2\/media?parent=1118"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}